1. Field of the Invention
The present invention relates to semiconductors and more particularly, to a semiconductor device and method for manufacturing the same.
2. Description of the Related Art
The improvement of performance of a semiconductor device has become a persistent demand in the field of semiconductors and integrated circuits. As the scaling of the semiconductor device and integrated circuit (IC) has become increasingly difficult, methods capable of improving semiconductor device performance without scaling of the semiconductor device have attracted attentions and concerns.
For example, in one method, a strained silicon technique is employed to apply stress in a semiconductor layer of a semiconductor device such as a transistor, so as to improve carrier mobility and thereby the semiconductor device performance. Generally, the above strained silicon technique may be implemented through SiGe epitaxy, Si—C epitaxy, and the like.
Application of localized source/drain isolation (also referred to as partially isolated semiconductors) transistors has been proposed. Such transistors are advantageous for suppressing the parasitic capacitance of a source/drain junction, reducing source and drain leakage current, etc.
For example, FIG. 1 shows a schematic structural diagram of a prior art localized source/drain isolated transistor 10.
As shown in FIG. 1, the transistor 10 comprises a semiconductor substrate 100 comprising, for example Si, a source/drain region 120 in the semiconductor substrate 100, a gate insulating film 130 on a channel region 115 of the semiconductor substrate 100, and a gate electrode 140 on the gate insulating film 130. In addition, the transistor 10 may further comprise a gate spacer 150, such as a nitride, around the gate electrode 140.
The source/drain region 120 is formed for example, from polycrystalline silicon. An isolation layer 110 is disposed below the source/drain region 120 and on a portion of a side of the source/drain region 120 interfacing with the channel region 115. The isolation layer 110 may be for example, silicon oxide. As shown in the figure, no isolation layer 110 is disposed at the portion of the side of the source/drain region 120 adjacent to the surface 105 of the semiconductor substrate 100. In this example, the source/drain region 120 is partially isolated from the semiconductor substrate 100 by the isolation layer 110, and is electrically connected to the channel region 115, thus forming a partially isolated source/drain region.
However, in such partially isolated source/drain devices, it is difficult to employ the existing strained silicon technique, since the source/drain region 120 is isolated by the isolation layer 110. For instance, in the case of source/drain region formed by polycrystalline silicon, it is difficult to produce stress in the channel direction through SiGe epitaxy and Si—C epitaxy, especially with a raised source/drain region.
Therefore, there is a continuing demand for an improved semiconductor device and method for manufacturing the same in the field of semiconductor devices.